Recent developments in fast semiconductor memories will lead to high speed signal transmission rates of for example up to 7 Gbit/s. These high signal transmission rates require careful design considerations with respect to the implementation of an appropriate topology and a suitable method of access of the memory chips on a memory module from a memory controller.
Enclosed FIG. 1 depicts a functional block diagram of an example of a heretofore known shared loop architecture which is a possible solution how to arrange a certain number of memory chips (for example DRAM chips) on a memory module 100 considering the connection to a memory controller 150. On the memory module 100 (for example a DIMM) for memory chips (or memory ranks) 110, 120, 130, 140 are arranged in such a way, that a command and data signal stream CawD is transferred from the memory controller 150 through a first transfer channel 102 to a first memory chip 110, from the first memory chip 110 through a second transfer channel 112 to a second memory chip 120, from the second memory chip 120 through a third transfer channel 122 to a third memory chip 130 from the third memory chip 130 through a fourth transfer channel 132 to a fourth memory chip 140 and from the fourth memory chip 140 through a fifth transfer channel 142 back to the memory controller 150.
In the above example of a shared loop architecture the memory module 100 may be a DIMM on which, for example, four DDR-DRAM memory chips having the same functionality are arranged. Data and command signals in the signal stream CawD are protocol-based and the connecting lines forming the transfer channels are connecting the DDR-DRAMs in the consecutive order as mentioned above and depicted in FIG. 1. That is, data and command signal stream CawD can only flow in one direction.
A further heretofore known example of a star topology architecture which is also appropriate for arranging memory chips on a memory module 200 and connecting the same to a memory controller 250 is illustrated in the functional block diagram of the enclosed FIG. 2. Four memory chips, for example, DDR-DRAM chips 210, 220, 230 and 240 are arranged on the memory module 200 in such a way that a command and data signal stream CawD is transferred from the memory controller 250 to one dedicated memory chip 210, in the following called “master” memory chip and from there back to the memory controller 250 (read data rD). Further, the command and data signal stream CawD can be transferred from the master memory chip 210 to a first memory chip 220 or a second memory chip 230 or a third memory chip 240 and from there back to the master memory chip 210. Like in the shared loop architecture depicted in FIG. 1 the data and command signals of the signal stream CawD in the star topology illustrated in FIG. 2 are protocol-based.
Since the memory chips on the exemplified memory modules 100 and 200 illustrated in FIGS. 1 and 2 must be accessed very flexible, there must be the possibility to perform certain operations, for example set-up operations in advance, i.e. before the actual command and data stream on the protocol basis has reached the memory chip. Especially the memory chips 110, 120, 130 and 140 in the shared loop topology illustrated in FIG. 1 and the master memory chip 210 in the star topology illustrated in FIG. 2, have/has to separate very fast and easily between re-drive and data processing tasks. Further, power consumption and related thermal effects are critical issues in both the shared loop topology and the star topology. The overall power consumption has to be kept as low as possible.
Up to now a proposal exists to transfer a rank select command or a clock enable command or even no clock enable command within a protocol-based frame on the regular command and data stream. This is very inflexible, because
a) the frame must be decoded to find out what is the rank select information or the clock enable information, i.e. which memory chip is addressed, for example the first memory chip 110, the second memory chip 120, the third memory chip 130 or the fourth memory chip 140 in the shared loop topology according to FIG. 1, or in the star topology according to FIG. 2 the master memory chip 210, the memory chip 220, the memory chip 230 or the memory chip 240 for data processing, for re-driving or for a low power stand-by mode;
b) the memory chips cannot be accessed in advance for certain set-up procedures or for certain power related procedures;
c) the memory chips cannot be accessed independently from the command and data stream;
d) the memory chips in the shared loop topology according to FIG. 1 and the master memory chip 210 in the star topology according to FIG. 2 have to separate between re-drive vs. memory chip read/write procedures—with a protocol included rank select, this leads to a higher logical effort;
e) because the rank select command and the clock enable information have to be decoded when they are included in the protocol, the main blocks in the chip are involved—even if only a re-drive has to be performed in a memory chip and therefore power consumption increases.